1. Field of the Invention
The present invention relates to a method for producing a semiconductor device, and more particularly relates to a method for producing a semiconductor device having fine contacts.
2. Description of the Related Art
Along with the advances made in higher integration and enhancement of performance of semiconductor devices as seen in very large scale integrated circuits (VLSI) etc. in recent years, the associated technical factors have been becoming increasingly stringent including factors such as dry etching of silicon oxide (SiO.sub.2)-based material layers.
In the midst of all of this, the self aligned contact (hereinafter abbreviated as SAC) technique which eliminates the need for a design margin on the mask for positioning of contact holes is attracting attention.
There has been active development of the SAC technique particularly in the 0.25 .mu.m rule generation and on. There are several reasons behind this. One is the limitation due to the performance of the exposure apparatus, while another is the positive reduction of chip and cell areas made possible by the use of SAC.
Particularly, the former means that it has become difficult to maintain the trend toward miniaturization of interconnection layers using the recently announced 0.25 .mu.m rule for mass production use exposure apparatuses. This is caused by the insufficient improvement of precision of positioning in steppers. Since the error in positioning is large, the design margin of the positioning also is large. As a result, the interconnections become wider or openings cannot be formed since the hole diameters become too small. Signs of this had already started to be seen from the 0.3 .mu.m rule. This problem cannot be avoided in the 0.25 to 0.2 .mu.m rules.
The technique which reportedly could eliminate the need for a design margin in positioning is SAC. There are several methods for SAC formation. All of them generally have the defect that the process becomes somewhat more complex in comparison with a related art method using only exposure. However, adoption of SAC is indispensable in the future. Various studies have been made concerning SAC.
An explanation will next be made of an example of the method of SAC formation with reference to FIGS. 1A and 1B. First, an explanation will be made of the semiconductor device shown in FIG. 1A. At an upper layer of a silicon semiconductor substrate 10, a gate electrode 30 comprising a lower gate electrode 30a of polycrystalline silicon and an upper gate electrode 30b of a tungsten silicide is formed via a gate insulating film 20, an offset insulating film 24 of a silicon oxide is formed at an upper layer thereof, and sidewall mask layers 25 (acting as spacers for forming a lightly doped drain (LDD) diffusion layer mentioned later) of silicon oxide are formed at the two side portions of the gate electrode 30 Further, in the semiconductor substrate 10 at the two side portions of the gate electrode 30, an LDD diffusion layer 11 containing a conductive impurity at a low concentration and a source and drain diffusion layer 12 containing them at a high concentration are formed, and a MOS field effect transistor is formed as described above. Further, an etching stopper film 21 made of for example a silicon nitride (Si.sub.3 N.sub.4) is formed over the entire surface by covering the offset insulating film 24 and the sidewall mask layer 25. At an upper layer thereof, an insulating film 22 of for example silicon oxide is formed.
When forming a contact hole in the semiconductor device, as shown in FIG. 1B, the contact hole CH is formed by forming a resist film R of a contact hole pattern at an upper layer of the insulating film 22 and etching the same by for example reactive ion etching (RIE). At this time, the etching is stopped once at a point of time when the etching stopper film 21 is exposed, then etching is carried out again under different conditions from those of the above etching to form a contact hole reaching the semiconductor substrate 10. According to this method, the number of exposure steps is not increased in comparison with the method of the related art not using SAC, therefore the rise in costs is relatively small. Further, the gate electrode 30 is covered by the etching stopper film 21 of silicon nitride, so the design margin of the positioning becomes unnecessary and it becomes possible to positively reduce the surface area of the chip and cell.
However, in order to put SAC using silicon nitride into practical use, it becomes necessary to develop a highly complex etching technique. At this time, it is necessary to cause the etching to stop at the thin silicon nitride film (etching stopper film 21) by using etching having a high selectivity with respect to silicon nitride, but as shown in for example FIG. 1B, a CF-based deposit 26 will be formed at the bottom portion of the contact hole during the etching. This CF-based deposit 26 is hard to be removed by etching. When the cell area is reduced and the distance between the gate electrodes 30 is reduced, a large amount of CF-based deposit 26 is formed causing an extreme microloading effect referred to as an "etch stop", thus it becomes impossible to form a contact hole.
In order to avoid this problem, the SAC structure shown in FIGS. 2A and 2B has been developed. First, an explanation will be made of the semiconductor device with reference to FIG. 2A. At the upper layer of the silicon semiconductor substrate 10, a gate electrode 30 comprising a lower gate electrode 30a of polycrystalline silicon and an upper gate electrode 30b of tungsten silicide is formed via a gate insulating film 20, an offset insulating film 24 of silicon nitride is formed at an upper layer thereof, and sidewall mask layers 25 of silicon nitride are formed in the two side portions of the gate electrode 30. Further, in the semiconductor substrate 10 at the two side portions of the gate electrode 30, an LDD diffusion layer 11 containing a conductive impurity at a low concentration and a source and drain diffusion layer 12 containing them at a high concentration are formed and a MOS field effect transistor is formed as described above. At an upper layer thereof, an insulating film 22 of for example silicon oxide is formed. In this structure, the offset insulating film 24 and the sidewall mask layer 25 are formed by silicon nitride and are made to act also as etching stopper films.
When forming a contact hole in the semiconductor device, as shown in FIG. 2B, a resist film R of the contact hole pattern is formed at an upper layer of the insulating film 22, then etched by, for example, RIE (reactive ion etching) to form the contact hole CH. At this time, it becomes possible to form a sufficiently stable SAC by the difference in thickness of the offset insulating film 24 and the sidewall mask layer 25 acting as the etching stopper films from the etching stopper film of the semiconductor device shown in FIGS. 1A and 1B even if the selectivity with respect to silicon nitride is not excessively increased. However, in this structure as well, in the 256 Mb dynamic random access memory (DRAM) class generation, the distance between gate electrodes is short, the opening portion exhibits a slit state, and the risk of etch stop is no longer much different from that of the semiconductor device shown in FIGS. 1A and 1B.
In order to solve the problem of etch stop, a method of removing the sidewall mask layer making the distance between the gate electrodes narrow after forming the diffusion layer of the LDD structure has been developed.
An explanation will next be made of the method for removing the sidewall mask layer by referring to FIGS. 3A and 3B. First, an explanation will be made of the semiconductor device with reference to FIG. 3A. At an upper layer of a silicon semiconductor substrate 10, a gate electrode 30 comprising a lower gate electrode 30a of polycrystalline silicon and an upper gate electrode 30b of tungsten silicide are formed via a gate insulating film 20. By covering the gate electrode 30, an etching stopper film 21 of for example silicon oxide is formed. Silicon-based sidewall mask layers 31c are formed at both side portions of the gate electrode 30 via this etching stopper film 21. This becomes the spacer for forming the LDD diffusion layer mentioned later. In the semiconductor substrate 10 at the two side portions of the gate electrode 30, an LDD diffusion layer 11 containing a conductive impurity at a low concentration and a source and drain diffusion layer 12 containing them at a high concentration are formed, and a MOS field effect transistor is formed as described above.
The semiconductor device is etched by for example plasma etching of the down flow type to selectively remove the sidewall mask layer 31c controlling the ratio of etching rate between the sidewall mask layer 31c and the etching stopper film 21. In the following steps, usually a thick inter-layer insulating film made of for example silicon oxide is formed over the entire surface covering the transistor, a contact hole penetrating through the inter-layer insulating film and reaching the semiconductor substrate 10 is formed, a plug is filled in the contact hole, an upper layer interconnection is formed, and so on to form the intended semiconductor device.
In forming the contact hole, even if the distance between the gate electrodes 30 becomes narrower by removing the sidewall mask layer 31c, there is no longer any obstacle in the SAC or other contact opening portion and the etch stop can be prevented. Further, the etching stopper film 21 is formed by covering an active region of the semiconductor substrate 10 and an element isolation region such as a not illustrated local-oxidation-of-silicon (LOCOS) film. Therefore, when removing the sidewall mask layer 31c, there is little chance of damage due to the etchant ions directly abutting against the semiconductor substrate or etching of the "bird's beak" etc. of the LOCOS film, which greatly contributes to improvement of device characteristics such as the leak current. As the sidewall mask layer which can be removed, those other than a silicon-based layer are also possible.
However, in the method for removing the sidewall mask layer as described above, there is the following problem. This will be explained by referring to FIGS. 3A and 33. As shown in the semiconductor device illustrated in FIG. 3A, after forming the sidewall mask layer 31c, the sidewall mask layer 31c acting as the LDD spacer is used as a mask to ion-implant a conductive impurity of a high concentration into the semiconductor substrate 10 and form the source and drain diffusion layer 12. The impurity ions at this time penetrate through the etching stopper film 21 and are implanted into the substrate. If the etching stopper film 21 is made thin in order to enhance the control of the ion implantation at this time, then when the sidewall mask layer 31c is removed by isotropic etching or the like, part of the etching stopper film 21 is removed before the removal of the sidewall mask layer 31c is terminated as shown in FIG. 3B. That is, irrespective of the fact that an etching remainder 31d exists, part of the etching stopper film 21 is removed, an opening portion H penetrating to the substrate 10 is formed, and a gouge in the substrate 10 is sometimes created.
The above problem occurs more conspicuously if an amorphous silicon excellent in step coverage is used as the sidewall mask layer since an amorphous silicon has a slow etching rate.